1. Field
The embodiments discussed herein are related to a method for manufacturing semiconductor devices which facilitate miniaturization, and a method for designing photomask patterns.
2. Description of the Related Art
In line with the requirement for miniaturization of semiconductor devices, recently the width of gate electrodes and the like has also been required to be smaller than a wavelength of exposure light used in patterning and positive-type resists have been mainly used in such an exposing step. However, for features smaller than the wavelength of the exposure light, proximity effects considerably appear when a resist pattern is formed and may result in differences between a pattern of a reticle and a pattern of a resist transferred from the reticle. Accordingly, a technique for compensating for the differences is applied, in which serifs on line ends of a reticle pattern, which are called hammer-heads, are provided in order to form a desired resist pattern.
To reduce the proximity effects, optical proximity correction (OPC) has been used, and this technique can be used to suppress variation of linewidth of patterns. However, the technique cannot also improve resolution. Therefore, to enhance the resolution, techniques of super-resolution are occasionally applied. Examples of super-resolution techniques include a technique using a phase-shift mask such as a Levenson-type mask and a technique using oblique illumination such as zone plate illumination.
However, in a case in which two conductive line ends face each other or a line end faces the side of another line, there may be difficulties in using such super-resolution techniques to form a resist pattern, which is designed to have fine features as small as the wavelength of exposure light, with a sufficient lithography margin. As a result, short circuits may occur at gate electrodes and the like. For currently manufactured TEGs that include several billion minute transistors, short circuits are a serious problem even if a short circuit occurs in only one transistor among several billion transistors.
Japanese Laid-open Patent Publication No. 2004-103999 discloses a technique in which two exposing steps for patterning gate electrodes to be a desired shape are performed. These two steps are performed with different reticles under different optical conditions. However, if this technique is applied, a lithography margin, which is needed in at least one exposing step, may be undesirably reduced and defects may easily occur in a developing step, which may lead to short circuiting of the pattern.